Desparing
星期三, 十月 17, 2007
SiGe ?
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http://en.wikipedia.org/wiki/Silicon_germanium
SiGe allows CMOS logic to be integrated with heterojunction bipolar transistors, making it suitable for mixed-signal circuits. Heterojunction bipolar transistors have higher forward gain and lower reverse gain than homojunction bipolar transistors. This translates into better low current and high frequency performance. Being a heterojunction technology, the opportunity for band gap tuning exists which has normally been available only to compound semiconductors. Silicon Germanium-on-insulator (SGOI) is a technology similar to the Silicon-On-Insulator (SOI) technology currently employed in computer chips. SGOI increases the speed of the transistors inside microchips by stretching the space between the atoms, which forces the electricity to travel faster.
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http://www.theregister.co.uk/2004/04/20/amd_strained_silicon/
Intel already uses strained silicon in its 90nm process, which debuted with the launch of 'Prescott' Pentium 4 desktop CPUs in February. The technique works by adding a layer of silicon over a layer of silicon germanium (SiGe). The top layer's silicon atoms align themselves with those in the SiGe layer's wider-spaced crystal lattice, pulling them apart. Wider spaced silicon atoms make for a smoother flow of electrons between them, improving the material's electrical properties.

Adding that SiGe layer into an existing fabrication process is tricky - it's almost certainly one of the reasons Intel took longer than planned to roll out its 90nm chips.

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http://www.theregister.co.uk/2003/09/09/ibm_boffins_boost_chip_performance/
The strained silicon technique - currently being used by Intel to make its upcoming 90nm processors, Prescott and Dothan - improves the electrical efficiency of on-chip circuits by stretching a layer of silicon over a layer of silicon germanium (SiGe). The top layer's silicon atoms align themselves with those in the SiGe layer's wider-spaced crystal lattice, stretching them apart. This improves the flow of electrons through the 'strained' silicon layer.

That, in turn, yields a 20-30 per cent improvement in circuit performance, said IBM, but adding the SiGe layer means the circuits are harder to make and tricky to integrate into existing fabrication processes. That's probably why Intel waited until moving to 90nm before implementing the technique.

To avoid the implementation issues, IBM tried using its established SOI technology in place of SiGe. IBM uses an SiGe layer to strain the silicon lattice, but removes it before fabrication, after applying the strained silicon onto the insulator. The upshot: it gains benefits of strained silicon using what is essentially its standard SOI process. By removing the SiGe layer, it doesn't have to integrate that material into the chip fabrication process per se. It calls the new technique, Strained Silicon Directly on Insulator (SSDOI).
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http://www.amdboard.com/65nm_120605.html
The companies announced that they have successfully combined embedded Silicon Germanium (e-SiGe) with Dual Stress Liner (DSL) and Stress Memorization technology (SMT) on Silicon-On-Insulator (SOI) wafers, resulting in a 40 percent increase in transistor performance compared to similar chips produced without stress technology, while controlling power consumption and heat dissipation. The new process technologies reduce interconnect delay through the use of lower dielectric constant (lower-K) insulators, which can improve overall product performance and lower power consumption. In addition, the new technologies have shown ability to be manufactured at the 65nm generation and scaleable for use in future generations.
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http://www.tomshardware.com/forum/191593-28-issue-65nm-shrink
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http://investorshub.advfn.com/boards/read_msg.asp?message_id=21353453
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http://www.commsdesign.com/story/OEG20020915S0001
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http://www.realworldtech.com/page.cfm?ArticleID=RWT121303010053&p=4
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IBM 500GHz SiGe
http://www.eetimes.com/news/semi/showArticle.jhtml?articleID=189500692
http://arstechnica.com/news.ars/post/20060622-7117.html
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40G photodetector: The other end of the link
http://blogs.intel.com/research/2007/09/40g_photodetector.html
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SSOI
http://www.eetimes.com/story/OEG20031222S0024
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Stretching silicon's lifespan
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http://www.theinquirer.net/en/inquirer/news/2006/03/08/not-all-cpus-are-created-equal
http://www.theinquirer.net/en/inquirer/news/2006/03/18/amd-fab-36-starts-to-ramp
http://www.theinquirer.net/en/inquirer/news/2006/06/09/amd-waits-for-65nm-to-crank-up-the-megahurts
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http://www.eetimes.com/showArticle.jhtml;jsessionid=AXIAAGFJ4LZC2QSNDLQSKICCJUNN2JVN?articleID=196701745
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